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static timing analysis

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  • Static timing analysis — is a method of computing the expected timing of a digital circuit without requiring simulation. High performance integrated circuits have traditionally been characterized by the clock frequency at which they operate.Gauging the ability of a… …   Wikipedia

  • Statistical static timing analysis — Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, in recent years the increased variation in semiconductor devices and interconnect has introduced a… …   Wikipedia

  • Timing closure — is the process by which an FPGA or a VLSI design is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer. The term is also used for the goal that is achieved, when… …   Wikipedia

  • Dynamic timing verification — refers to verifying that an ASIC design is fast enough to run without errors at targeted clock rate. This is accomplished by simulating the design files used to synthesize the Integrated Circuit design. This is in contrast to static timing… …   Wikipedia

  • Continuous variable valve timing — offers a unique ability to have independent control of the intake and exhaust valves in an internal combustion engine. For any engine load criteria, the timing of intake and exhaust can be independently programmed [1]. The main variations of… …   Wikipedia

  • Object-oriented analysis and design — (OOAD) is a software engineering approach that models a system as a group of interacting objects. Each object represents some entity of interest in the system being modeled, and is characterised by its class, its state (data elements), and its… …   Wikipedia

  • Laban Movement Analysis — (LMA) is a system and language for understanding, observing, describing and notating all forms of movement. Devised by Rudolf Laban, LMA draws on his theories of effort and shape to describe, interpret and document human movement. Used as a tool… …   Wikipedia

  • Worst-case execution time — The worst case execution time (WCET) of a computational task is the maximum length of time the task could take to execute on a specific hardware platform. Knowing worst case execution times is of prime importance for the schedulability analysis… …   Wikipedia

  • Delay calculation — is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine …   Wikipedia

  • Simucad — Infobox Company company name = Simucad Design Automation, Inc. company company type = Private Company| foundation = 2004 location = key people = Dr Ivan Pesic, President/CEO Mr Marc Goldberg, Sales Contact industry = Software Programming homepage …   Wikipedia

  • Design closure — is the process by which a VLSI design is modified from its initial description to meet a growing list of design constraints and objectives. Every step in the IC design (such as static timing analysis, placement, routing, and so on) is already… …   Wikipedia

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